US 12,112,700 B2
Pixel circuit and driving method therefor, and display apparatus
Tianyi Cheng, Beijing (CN); Haigang Qing, Beijing (CN); Hongda Cui, Beijing (CN); Sifei Ai, Beijing (CN); Guowei Zhao, Beijing (CN); Yang Yu, Beijing (CN); Li Wang, Beijing (CN); and Baoyun Wu, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/273,788
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jul. 29, 2022, PCT No. PCT/CN2022/109160
§ 371(c)(1), (2) Date Jul. 24, 2023,
PCT Pub. No. WO2023/006100, PCT Pub. Date Feb. 2, 2023.
Claims priority of application No. PCT/CN2021/109884 (WO), filed on Jul. 30, 2021.
Prior Publication US 2024/0078976 A1, Mar. 7, 2024
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A pixel circuit, which is disposed in a display substrate, wherein the display substrate comprises a first drive mode and a second drive mode, a refresh rate of the first drive mode is less than that of the second drive mode, content displayed by the display substrate comprises a plurality of display frames, in the first drive mode and the second drive mode, a display frame comprises a refresh frame, in the pixel circuit, a compensation control circuit comprises a first transistor, a gate of the first transistor is electrically connected with a first scan line, a first initialization circuit comprises a second transistor, a gate of the second transistor is electrically connected with an initialization control line, a drain of the second transistor is electrically connected with a first initial voltage terminal, a reset circuit comprises a third transistor, a gate of the third transistor is electrically connected with a second scan line, a drain of the third transistor is electrically connected with a reset voltage terminal; a data writing circuit comprises a fourth transistor; a gate of the fourth transistor is electrically connected with a fourth scan line, a drain of the fourth transistor is electrically connected with a data line, and a second initialization circuit comprises a seventh transistor; a gate of the seventh transistor is electrically connected with a third scan line, a drain of the seventh transistor is electrically connected with a second initial voltage terminal, and a light emitting control circuit comprises a fifth transistor and a sixth transistor, gates of the fifth transistor and the sixth transistor are electrically connected with a light emitting control line;
a signal of the second scan line is the same as a signal of the third scan line, and time when the signal of the second scan line is an active level signal comprises a first refresh time period, a second refresh time period, and a third refresh time period which sequentially occur at intervals, during the second refresh time period, a signal of the first scan line is an inactive level signal;
a voltage of a signal of the reset voltage terminal is a positive voltage, a voltage of a signal of the first initial voltage terminal is a negative voltage, and a difference between the voltage of the signal of the reset voltage terminal and the voltage of the signal of the first initial voltage terminal is greater than a threshold difference.