| CPC G09G 3/3233 (2013.01) [G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] | 18 Claims |
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1. A pixel driving circuit comprising:
a pixel internal memory comprising a plurality of memory cells configured to store a setting value related to stored data comprising pixel driving data and video data;
a signal detection circuit comprising a row signal input terminal and a column signal input terminal;
a first low-pass filter configured to output a first signal, which has a first frequency lower than a preset first cutoff frequency, from a signal output from the signal detection circuit; and
a second low-pass filter configured to output a second signal, which has a second frequency lower than a preset second cutoff frequency, from the signal output from the signal detection circuit to the pixel internal memory,
wherein the pixel internal memory comprises:
a single flag memory cell configured to store a mode value;
a setting data shift register having a plurality of setting memory cells configured to store the setting value related to pixel driving; and
K video data shift registers corresponding to a number of light-emitting elements configured to store the video data.
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