US 12,112,673 B2
Display panel and display device
Chongyang Zhao, Beijing (CN); Yingmeng Miao, Beijing (CN); Zhihua Sun, Beijing (CN); Feng Qu, Beijing (CN); and Xiaochun Xu, Beijing (CN)
Assigned to Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/796,660
Filed by Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 10, 2021, PCT No. PCT/CN2021/099278
§ 371(c)(1), (2) Date Jul. 31, 2022,
PCT Pub. No. WO2022/022095, PCT Pub. Date Feb. 3, 2022.
Claims priority of application No. 202010763145.2 (CN), filed on Jul. 31, 2020.
Prior Publication US 2023/0335029 A1, Oct. 19, 2023
Int. Cl. G09G 3/20 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/20 (2013.01) [G11C 19/28 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/0286 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display panel, comprising p pixel unit groups, each of the p pixel unit groups comprising q rows of pixel units, both p and q being integers greater than or equal to 2; wherein pixel units in a same group are simultaneously supplied with a gate scan signal by a same shift register; and pixel units in a same group and in a same column are supplied with data voltage signals through different data lines, respectively;
the display panel further comprises N clock signal lines, N being an even number greater than or equal to 4, and p being greater than or equal to 2N; wherein each shift register is connected to one of the N clock signal lines, shift registers connected to different clock signal lines are different, and the q rows of pixel units in each group are adjacent to each other;
wherein pixel units in a same row are connected to a same gate line; each shift register comprises q shift register units, and the shift register units are connected to gate lines in one-to-one correspondence; and
wherein each shift register unit comprises a cascade signal output terminal and a signal output terminal, a signal output by the cascade signal output terminal and a signal output by the signal output terminal are the same as each other and are synchronous, the cascade signal output terminal is configured to be connected to a pull-up reset signal terminal of a shift register unit in a previous stage and a signal input terminal of a shift register unit in a next stage, and the signal output terminal is configured to be connected to a corresponding gate line.