US 12,112,399 B2
Low latency streaming remapping engine
Niraj Nandan, Plano, TX (US); Rajasekhar Reddy Allu, Plano, TX (US); and Mihir Narendra Mody, Bengaluru (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 8, 2021, as Appl. No. 17/520,861.
Application 17/520,861 is a continuation of application No. 16/909,710, filed on Jun. 23, 2020, granted, now 11,170,464.
Claims priority of provisional application 62/956,988, filed on Jan. 3, 2020.
Prior Publication US 2022/0058768 A1, Feb. 24, 2022
Int. Cl. G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/60 (2013.01) [G06F 9/5027 (2013.01); G06F 9/5066 (2013.01); G06F 9/544 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device comprising:
a first memory configured to store a frame of input image data that includes a first subset of the frame;
a second memory configured to store output image data that includes a first block associated with the first subset of the frame;
first and second schedulers coupled to the first memory, wherein the first scheduler is configured to provide to the second scheduler a notification associated indicating that the first block is ready for processing the second scheduler receiving an indication that space for at least the first block is available in the second memory;
an image processing circuit coupled to the first memory, the second memory, and the second scheduler, wherein the image processing circuit is configured to, based on the notification:
prior to the first memory completely storing the frame of input image data, read the first subset of the frame from the first memory;
process the first subset of the frame to produce the first block; and
provide the first block for storing by the second memory.