| CPC G06N 20/00 (2019.01) [G01R 31/2882 (2013.01)] | 5 Claims |
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1. A method for manufacturing an integrated circuit based on a prediction of a fluctuation of circuit path delay on the basis of machine learning, comprising the following steps:
S1: selecting suitable sample characteristics by means of analyzing a relationship between circuit characteristics and a path delay;
S2: generating a random path by means of enumerating values of randomized parameters, acquiring a maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3σ standard, and using the sample characteristics and the path delay of the reliable path as a sample set;
S3: establishing a path delay prediction model, and adjusting parameters of the path prediction model;
S4: verifying a precision and a stability of the path delay prediction model;
S5: obtaining an output path delay;
S6: generating a layout of the integrated circuit based on the output path delay; and
S7: manufacturing the integrated circuit based on the layout, wherein the path delay prediction model in step S3 is established by the following sub-steps:
S3.1: randomly selecting n samples in a returnable manner from data in a training set, and using the samples as the training set for generating a regression tree;
S3.2: generating an unpruned regression tree for each sample, and modifying the regression tree; and performing random sampling of prediction variables at each node of the unpruned regression tree, and selecting an optimum segmentation point from these prediction variables; and
S3.3: establishing the path delay prediction model by data clustering of n unpruned regression trees to predict a new path delay, and using an average value of clustering results as the output path delay by the path delay prediction model.
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