US 12,112,204 B2
Modular accelerator function unit (AFU) design, discovery, and reuse
Pratik M. Marolia, Hillsboro, OR (US); Aaron J. Grier, Hillsboro, OR (US); Henry M. Mitchel, Wayne, NJ (US); Joseph Grecco, Saddle Brook, NJ (US); Michael C. Adler, Newton, MA (US); Utkarsh Y. Kakaiya, Folsom, CA (US); Joshua D. Fender, East York (CA); Sundar Nadathur, Cupertino, CA (US); and Nagabhushan Chitlur, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 9, 2022, as Appl. No. 17/884,244.
Application 17/884,244 is a continuation of application No. 16/619,442, granted, now 11,416,300, previously published as PCT/US2017/039880, filed on Jun. 29, 2017.
Prior Publication US 2023/0070995 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/50 (2006.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 9/468 (2013.01); G06F 9/4843 (2013.01); G06F 9/5044 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An apparatus comprising:
function unit circuitry to implement at least a first function; and
one or more device feature header (DFH) registers to store attributes associated with the function unit circuitry,
wherein a DFH register is to at least store:
an identifier associated with the function unit circuitry,
a type description of the function unit circuitry,
an indication of a location of a next DFH register, and
a size of a corresponding memory-mapped input/output (MMIO) region.