US 12,112,171 B2
Loop support extensions
Anant Nori, Bangalore (IN); Shankar Balachandran, Bangalore (IN); Sreenivas Subramoney, Bangalore (IN); Joydeep Rakshit, Bengaluru (IN); Vedvyas Shanbhogue, Austin, TX (US); Avishaii Abuhatzera, Amir (IL); and Belliappa Kuttanna, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 26, 2020, as Appl. No. 17/134,367.
Claims priority of provisional application 63/083,902, filed on Sep. 26, 2020.
Prior Publication US 2022/0100514 A1, Mar. 31, 2022
Int. Cl. G06F 8/41 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30065 (2013.01); G06F 9/3836 (2013.01); G06F 9/4881 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be:
placed into code storage after being decoded,
unrolled and scheduled from the code storage using an unroll scheduler, and
placed into one or more issue queues for execution; and
the execution circuitry to perform the operation as indicated by the opcode.