US 12,112,169 B2
Register freeing latency
Luca Nassi, Antibes (FR); Geoffray Matthieu Lacourba, Nice (FR); Cédric Denis Robert Airaud, Saint Laurent du Var (FR); and Albin Pierrick Tonnerre, Nice (FR)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jan. 12, 2023, as Appl. No. 18/096,141.
Prior Publication US 2024/0241723 A1, Jul. 18, 2024
Int. Cl. G06F 13/40 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30098 (2013.01) [G06F 9/30094 (2013.01); G06F 9/384 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A data processing apparatus comprising:
instruction send circuitry configured to send an instruction to an external processor to be executed by the external processor;
allocation circuitry configured to allocate a specified one of a plurality of registers for a result of the instruction having been executed on the external processor; and
data receive circuitry configured to receive the result of the instruction having been executed on the external processor and to store the result in the specified one of the plurality of registers, wherein
in response to a condition being met:
the specified one of the plurality of registers is dereserved prior to the result being received by the data receive circuitry, and the result is discarded by the data receive circuitry when the result is received by the data receive circuitry.