US 12,112,168 B1
Method for processing multiple transactions converted from single transaction in processor, and processor for performing same
Kwang Sun Lee, Yongin-si (KR); Do Hun Kim, Yongin-si (KR); and Kee Bum Shin, Yongin-si (KR)
Assigned to MetisX CO., Ltd., Yongin-si (KR)
Filed by MetisX CO., Ltd., Yongin-si (KR)
Filed on Apr. 24, 2024, as Appl. No. 18/644,249.
Claims priority of application No. 10-2023-0093167 (KR), filed on Jul. 18, 2023.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30047 (2013.01) [G06F 9/30043 (2013.01); G06F 9/3009 (2013.01); G06F 9/3004 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for processing multiple transactions converted from a single transaction for each thread of a plurality of threads, the method being performed by a processor including at least one core and comprising:
converting a first transaction related to at least one of the plurality of threads into a plurality of second transactions;
transferring, by a load-store unit (LSU) of the core, the plurality of second transactions to a subordinate or a cache;
receiving, by the LSU, a plurality of data units related to the second transactions from the subordinate or the cache; and
merging, by the LSU, the plurality of data units,
wherein the LSU is configured to further transfer interleaving deactivation information that causes the subordinate or the cache to deactivate interleaving.