US 12,112,167 B2
Matrix data scatter and gather between rows and irregularly spaced memory locations
Christopher J. Hughes, Santa Clara, CA (US); Alexander F. Heinecke, San Jose, CA (US); Robert Valentine, Kiryat Tivon (IL); Menachem Adelman, Haifa (IL); Evangelos Georganas, San Mateo, CA (US); Mark J. Charney, Lexington, MA (US); Nikita A. Shustrov, Novosibirsk (RU); and Sara Baghsorkhi, Los Gatos, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 27, 2020, as Appl. No. 16/914,321.
Prior Publication US 2021/0406016 A1, Dec. 30, 2021
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30043 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/30098 (2013.01); G06F 9/30145 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor comprising:
storage for a matrix;
a decoder to decode an instruction having a format including an opcode field to specify an opcode and a first operand field to specify a set of irregularly spaced memory locations by specifying a set of indices, the set of indices including at least one index having a reserved value; and
execution circuitry to, in response to the decoded instruction, calculate a set of addresses corresponding to the set of irregularly spaced memory locations and transfer a set of rows of data between the storage and the set of irregularly spaced memory locations, wherein the reserved value is to indicate that a corresponding row is to be skipped or zeroed.