US 12,112,164 B2
Machine code instruction
Alan Alexander, Wotton-Under-Edge (GB); Simon Knowles, Bristol (GB); Godfrey Da Costa, Bristol (GB); and Badreddine Noune, Bristol (GB)
Assigned to GRAPHCORE LIMITED, Bristol (GB)
Filed by Graphcore Limited, Bristol (GB)
Filed on Feb. 28, 2023, as Appl. No. 18/176,034.
Claims priority of application No. 2202794 (GB), filed on Mar. 1, 2022.
Prior Publication US 2023/0281013 A1, Sep. 7, 2023
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30014 (2013.01) [G06F 9/3013 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A processing device comprising:
a plurality of operand registers, wherein a first subset of the operand registers is configured to store state information for a plurality of bins, wherein for each of the plurality of bins, the state information comprises a range of values and a bin count associated with a respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and
an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for a first floating-point value of the vector:
identify, based on an exponent of the first floating-point value, a first bin of the plurality of bins for which the first floating-point value falls within an associated range of values for the first bin; and
increment a first bin count associated with the first bin.