US 12,112,143 B2
Multiplication and accumulation circuit based on radix-4 booth code and differential weight
Kejie Huang, Zhejiang (CN); Rui Xiao, Zhejiang (CN); and Haibin Shen, Zhejiang (CN)
Assigned to ZHEJIANG UNIVERSITY, Zhejiang (CN)
Appl. No. 17/274,962
Filed by ZHEJIANG UNIVERSITY, Zhejiang (CN)
PCT Filed May 26, 2020, PCT No. PCT/CN2020/092286
§ 371(c)(1), (2) Date Mar. 10, 2021,
PCT Pub. No. WO2020/238889, PCT Pub. Date Dec. 3, 2020.
Claims priority of application No. 201910462374.8 (CN), filed on May 30, 2019.
Prior Publication US 2021/0365241 A1, Nov. 25, 2021
Int. Cl. G06F 7/544 (2006.01); H03M 3/04 (2006.01); G06N 3/04 (2023.01); G11C 13/00 (2006.01)
CPC G06F 7/5443 (2013.01) [H03M 3/04 (2013.01); G06N 3/04 (2013.01); G11C 13/0002 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A multiplication and accumulation circuit based on radix-4 booth code and differential weight storage, comprising: an input data encoding circuit, a differential weight storage circuit, an integral calculation circuit and a differential analog-to-digital converters (ADC) circuit, wherein output of the input data encoding circuit is sent into the differential ADC circuit after sequentially passing through the differential weight storage circuit, wherein:
the input data encoding circuit is configured to encode original input data;
the differential weight storage circuit is configured to store weight values, and multiply the original input data after being encoded by the weight values stored to obtain multiplication results;
the integral calculation circuit is configured to respectively accumulate positive values and negative values of respective multiplication results; and
the differential ADC circuit is configured to perform analog-to-digital conversion on a difference between accumulated positive values and accumulated negative values to obtain a digital multiplication and accumulation result;
wherein the differential weight storage circuit comprises two weight storage circuits with equal size, each of the weight storage circuits comprises a plurality of basic units, each of the basic units comprises a transistor and a binary resistive random-access- memory (RRAM) coupled in series, one end of the binary RRAM is coupled to a source of the transistor, the other end of the binary RRAM is grounded; a gate of the transistor is coupled to an output end of the input data encoding circuit, and a drain of the transistor is configured as an output end of the basic unit and coupled to an input end of the integral calculation circuit, the drains of the transistors of the basic units in the same column are coupled to each other, and the gates of the transistors of the basic units in the same row are coupled to each other and configured as an input end of the basic unit.