CPC G06F 30/392 (2020.01) [G03F 1/70 (2013.01); G06F 30/398 (2020.01); G06F 2111/20 (2020.01)] | 20 Claims |
1. A computer-implemented method comprising:
placing a plurality of shapes within a hierarchical level of a chip design having two or more edge cells and one or more internal cells, the plurality of shapes comprising a top boundary shape common to at least two cells of the two or more edge cells and the one or more internal cells, a bottom boundary shape common to the at least two cells of the two or more edge cells and the one or more internal cells, one or more center boundary shapes, and one or more internal shapes, the one or more center boundary shapes positioned at boundaries of the two or more edge cells and internal cells midway between the top boundary shape and the bottom boundary shape;
pinning the top boundary shape to a first mask;
pinning the bottom boundary shape to a second mask; and
pinning the one or more center boundary shapes to a same mask, wherein the same mask is selected from one of the first mask and the second mask.
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