US 12,112,113 B2
Complementary die-to-die interface
Sergio Kolor, Haifa (IL); Dany Davidov, Tirat Carmel (IL); Nir Leshem, Beit Yanai (IL); Mark Pilip, Kiryat Bialik (IL); and Lior Zimet, Kerem Maharal (IL)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 5, 2021, as Appl. No. 17/194,003.
Prior Publication US 2022/0284163 A1, Sep. 8, 2022
Int. Cl. G06F 30/392 (2020.01); G06F 13/40 (2006.01); G06F 115/02 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 13/4068 (2013.01); G06F 2115/02 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a first instance of a particular integrated circuit die having a die-to-die interface with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry; and
a second instance of the particular integrated circuit die having the die-to-die interface;
wherein the die-to-die interfaces of the first and second instances of the particular integrated circuit die are coupled such that conductive paths from the transmit and receive pins for the particular bus on the first instance are aligned, respectively, to receive and transmit pins for the particular bus on the second instance without crossing.