| CPC G06F 30/3312 (2020.01) [G06F 30/337 (2020.01); G06F 2111/08 (2020.01); G06F 2119/22 (2020.01)] | 10 Claims |
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1. A method for computing timing yield for an integrated circuit (IC) having a plurality of timing arcs and endpoints, a plurality of subsets of the timing arcs, each subset associated with an endpoint, the method comprising:
a) generating a speed index associated with each timing arc of a first IC sample to determine a random delay value, wherein the same speed index is used for common timing arcs to determine the random delay values for different signal paths through the common timing arcs of an element of the integrated circuit;
b) generating a first delay sample for each timing arc of the first IC sample based on the associated speed index, a delay distribution of the timing arc and a path context;
c) determining a slack for each endpoint of the first IC sample;
d) determining the worst slack from among the slacks determined for the first IC sample;
e) repeating a) through d) for a plurality of IC samples; and
f) determining timing yield for the IC based on the ratio of the number of determined worst slacks that have a non-negative value with respect to the total number of IC samples.
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