US 12,112,071 B2
Nonvolatile memory device supporting high-efficiency I/O interface
Seonkyoo Lee, Hwaseong-si (KR); Jeongdon Ihm, Seongnam-si (KR); Chiweon Yoon, Seoul (KR); and Byunghoon Jeong, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 30, 2023, as Appl. No. 18/217,063.
Application 18/217,063 is a continuation of application No. 17/828,176, filed on May 31, 2022, granted, now 11,714,579.
Application 17/828,176 is a continuation of application No. 17/168,620, filed on Feb. 5, 2021, granted, now 11,372,593, issued on Jun. 28, 2022.
Claims priority of application No. 10-2020-0086227 (KR), filed on Jul. 13, 2020.
Prior Publication US 2023/0342085 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 1/06 (2006.01); G06F 13/16 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 1/06 (2013.01); G06F 3/0613 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
a memory interface circuit configured to:
receive, from a memory controller via first signal lines, a first control signal and a second control signal during a first cycle period and a second cycle period from among time periods included in a predetermined number of cycle periods,
receive a write enable signal from the memory controller via a second signal line,
obtain a command from the first control signal and the second control signal received during remaining cycle periods of the time periods based on a toggle timing of the write enable signal, when the first control signal and the second control signal received during the first and the second cycle periods are in a first state, and
obtain an address from the first control signal and the second control signal received during the remaining cycle periods based on a toggle timing of the write enable signal, when the first control signal and the second control signal received during the first and the second cycle periods are in a second state.