US 12,112,067 B2
Persistent xSPI STT-MRAM with optional erase operation
Syed M. Alam, Austin, TX (US); Iftekhar Rahman, Chandler, AZ (US); and Pedro Sanchez, Chandler, AZ (US)
Assigned to Everspin Technologies, Inc., Chandler, AZ (US)
Filed by Everspin Technologies, Inc., Chandler, AZ (US)
Filed on Aug. 9, 2022, as Appl. No. 17/884,040.
Claims priority of provisional application 63/269,660, filed on Mar. 21, 2022.
Prior Publication US 2023/0297283 A1, Sep. 21, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0673 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for programming a memory device comprising a plurality of memory arrays and a non-volatile erase bit value register, the method comprising:
receiving a command to program one or more of the plurality of memory arrays; and
programming the one or more of the plurality of memory arrays based on the command, wherein the method comprises optionally erasing the one or more of the plurality of memory arrays prior to the programming,
wherein the optionally erasing the one or more of the plurality of memory arrays comprises:
if a performance or an operation time is critical, assigning an erase bit value in the erase bit value register a first state, or
if the performance or operation time is not critical, assigning the erase bit value in the erase bit value register a second state; and
receiving the erase bit value from the erase bit value register, wherein, when the erase bit value is in the first state, an optional erase command is activated such as to erase the one or more of the plurality of memory arrays, and, when the erase bit value is in the second state, an optional erase command is not activated such as not to erase the one or more of the plurality of memory arrays.