US 12,112,063 B1
Reordering memory controller
Michael Thomas Imel, Beaverton, OR (US); Larry Arbuthnot, Portland, OR (US); and Charles J. Wilson, Portland, OR (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/481,851.
Claims priority of provisional application 63/149,200, filed on Feb. 12, 2021.
Claims priority of provisional application 63/105,531, filed on Oct. 26, 2020.
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0673 (2013.01); G06F 13/1626 (2013.01); G06F 13/1631 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for queuing memory operation requests in a memory controller, the method comprising:
storing a queue of memory operation requests ordered based on relative times of receipt in a fixed set of ordered request slots, the queue of memory operation requests associated with multiple different memory banks of a memory device;
storing respective status bits associated with each of the memory operation requests in the queue, the respective status bits indicating ordering constraints that constrain relative order of issuance of the memory operation requests in the queue;
receiving a new request in an input register;
selecting in a given memory controller cycle, based on the respective status bits indicating the ordering constraints and relative positions of the memory operation requests in the fixed set of ordered request slots indicating the relative times of receipt, a selected request from the queue for issuing to the memory device;
updating the queue to remove the selected request from the queue to an output register, to shift to at least a subset of remaining requests between the ordered request slots such that a slot vacated by the selected request is filled, and to add the new request into the ordered request slots adjacent to the shifted subset of remaining requests, such that after updating, the requests in the queue are maintained in time order and are positioned in a compressed set of adjacent slots of the fixed set of ordered request slots;
issuing the selected request from the output register to a memory device; and
updating the respective status bits associated with remaining memory operation requests in the queue to add ordering constraints relating to the new request added to the queue and to remove ordering constraints relating to the selected request removed from the queue.