US 12,112,057 B2
Strategic memory cell reliability management
Marco Sforzin, Cernusco sul Naviglio (IT); and Daniele Balluchi, Cernusco sul Naviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 10, 2022, as Appl. No. 17/861,233.
Claims priority of provisional application 63/223,219, filed on Jul. 19, 2021.
Prior Publication US 2023/0016520 A1, Jan. 19, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
activating a set of memory cells in a memory device to perform a memory access, the memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device;
receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells, wherein the signaling comprises one or more bits that indicate whether to disable a flip operation on the set of memory cells;
performing the precharge operation on the set of memory cells based at least in part on the signaling; and
reading the set of memory cells subsequent to activating the set of memory cells and prior to pre-charging the set of memory cells.