| CPC G06F 3/0652 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/5635 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 2211/5642 (2013.01)] | 20 Claims |
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1. A non-volatile memory device, comprising:
a control logic circuit configured to generate a program signal based on a first control signal and to generate an erase signal based on a second control signal;
a voltage generator configured to generate a program voltage based on the program signal received from the control logic circuit and to generate an erase voltage based on the erase signal received from the control logic circuit, wherein the erase voltage is greater than the program voltage;
a memory cell array including a memory cell, a string select transistor coupled to the memory cell, a bit-line coupled to the string select transistor, and a string select line coupled to the string select transistor; and
a page buffer circuit coupled to the bit-line, and including a first precharge transistor that is configured to operate based on the program signal and the erase signal,
wherein the first precharge transistor is configured to:
when the string select transistor is programmed in response to the program signal, apply the program voltage to the bit-line, wherein the program voltage is greater than an internal power voltage of the page buffer circuit; and
when the memory cell is erased in response to the erase signal, apply the erase voltage to the bit-line.
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