| CPC G06F 3/0625 (2013.01) [G06F 3/0631 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01)] | 7 Claims |
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5. A self-managed dynamic random-access memory (DRAM) module, comprising:
a plurality of DDR channels, each DDR channel having a set of DRAM chips; and
a controller chip configured to read and write data blocks to DDR channels according to a process that includes:
allocating a set of sub-channels for each DDR channel, wherein each sub-channel includes a subset of the set of DRAM chips;
wherein a write operation of a data block includes:
encoding the data block to generate an ECC codeword;
determining whether the data block qualifies for data folding;
in response to the data block not qualifying for data folding, writing the ECC codeword into all of the DRAM chips of a DDR channel;
in response to the data block qualifying for data folding, writing the ECC codeword into the subset of DRAM chips of a specified sub-channel; and
wherein a read operation of the data block includes:
reading the ECC codeword from the subset of DRAM chips of the specified sub-channel; and
decoding the ECC codeword to obtain the data block.
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