US 12,112,048 B2
Adaptive tuning of memory device clock rates based on dynamic parameters
Shay Benisty, Beer Sheva (IL); Ariel Navon, Revava (IL); Alexander Bazarsky, Holon (IL); and David Avraham, Even Yehuda (IL)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Sep. 7, 2022, as Appl. No. 17/939,186.
Prior Publication US 2024/0078026 A1, Mar. 7, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller includes an adaptive frequency table that has different clock rates for different data storage device elements as a function of bit error rate (BER), wherein the controller is configured to:
assess system parameters;
determine that BER has changed;
select clock frequency operating parameters from the adaptive frequency table based upon the changed BER; and
update clock frequency of at least one controller component based upon the selected clock frequency.