at least one first data buffer module, at least one operation module, and at least one second data buffer module; wherein

the second data buffer module is configured to send a flow control count signal to the first data buffer module, the flow control count signal being used for informing the first data buffer module of an amount of data that can be received of the second data buffer module; and

the first data buffer module is configured to send a data signal and a valid signal to the second data buffer module via the operation modules in a first sequence according to the flow control count signal, the valid signal being used for indicating that the corresponding data signal is valid,

wherein the flow control count signal is a high-level signal, and each clock cycle that the high level of the flow control count signal lasts represents that one piece of data is receivable by the second data buffer module.