US 12,111,789 B2
Distributed graphics processor unit architecture
Dmitri Yudanov, Rancho Cordova, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 22, 2020, as Appl. No. 16/855,879.
Prior Publication US 2021/0334234 A1, Oct. 28, 2021
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 15/80 (2006.01); G06N 3/063 (2023.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06F 15/8092 (2013.01) [G06F 9/30043 (2013.01); G06F 9/3877 (2013.01); G06F 9/5083 (2013.01); G06N 3/063 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 31 Claims
OG exemplary drawing
 
1. A system comprising:
an array of processing nodes, each processing node comprising:
a vector-scalar processor (VSP), wherein the VSP can be re-configured to perform vector processing or scalar processing, the VSP comprising onboard memory via a vector arithmetic-logic unit (ALU) and a set of registers, wherein the vector ALU and the set of registers can be re-allocated when the vector ALU and set of registers are re-configured to operate on one of scalar or vector data inputs, wherein the vector ALU is re-configured by re-configuring the vector ALU into a combination of scalar processing elements and multiple vector processing elements, each size of the multiple vector processing elements smaller than a size of the scalar processing elements,
a Random Access Memory (RAM) unit coupled to the VSP, and
a non-volatile storage unit coupled to one of the VSP or the RAM unit; and
a driver comprising code to control the array of processing nodes to perform an operation by re-configuring the vector ALU to operate on one of scalar or vector data inputs and distributing an execution of the operation across at least a portion of the array of processing nodes.