US 12,111,784 B2
NoC buffer management for virtual channels
Krishnan Srinivasan, San Jose, CA (US); Abbas Morshed, Los Altos, CA (US); and Sagheer Ahmad, Cupertino, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Oct. 4, 2022, as Appl. No. 17/959,903.
Prior Publication US 2024/0111704 A1, Apr. 4, 2024
Int. Cl. G06F 13/40 (2006.01)
CPC G06F 13/4059 (2013.01) [G06F 13/4022 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first hardware circuit;
a second hardware circuit; and
a network on a chip (NoC) communicatively coupling the first hardware circuit and the second hardware circuit, the NoC comprising:
a plurality of switches, each switch comprising a plurality of ports, each port comprising a buffer,
wherein the buffer comprises a plurality of pods divided into multiple pod groups, at least a subset of the pod groups configured to be a different size, and each pod group assigned to a different virtual channel of a plurality of virtual channels based on a width of each of the plurality of virtual channels.