US 12,111,781 B2
Data burst suspend mode using multi-level signaling
Eric N. Lee, San Jose, CA (US); Leonid Minz, Beer Sheva (IL); Yoav Weinberg, Toronto (CA); Ali Feiz Zarrin Ghalam, Sunnyvale, CA (US); and Luigi Pilolli, L'Aquila (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 9, 2023, as Appl. No. 18/119,576.
Claims priority of provisional application 63/318,953, filed on Mar. 11, 2022.
Prior Publication US 2023/0289306 A1, Sep. 14, 2023
Int. Cl. G06F 13/30 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/30 (2013.01) [G06F 13/1668 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
processing logic, operatively coupled with the memory array, to perform operations comprising:
causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus;
causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode; and
causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.