US 12,111,780 B2
Multi-channel system architecture for managing flow of data and associated trace information
Mihir Narendra Mody, Bengaluru (IN); Ankur Ankur, New Delhi (IN); Vivek Vilas Dhande, Jalgaon (IN); Kedar Satish Chitnis, Bengaluru (IN); Niraj Nandan, Plano, TX (US); Brijesh Jadav, Bengaluru (IN); Shyam Jagannathan, Bengaluru (IN); Prithvi Shankar Yeyyadi Anantha, Bengaluru (IN); and Santhanakrishnan Narayanan Narayanan, Bengaluru (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 22, 2022, as Appl. No. 17/677,638.
Prior Publication US 2023/0267084 A1, Aug. 24, 2023
Int. Cl. G06F 13/28 (2006.01); G06F 9/48 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 15/78 (2006.01)
CPC G06F 13/28 (2013.01) [G06F 9/4881 (2013.01); G06F 13/1673 (2013.01); G06F 13/4221 (2013.01); G06F 15/7807 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system-on-chip comprising:
a first memory device;
a first interface;
a first processing resource communicably coupled to the first interface and the first memory device, the first processing resource comprising:
a data buffer; and
a first direct memory access (DMA) controller configured to:
transmit data from the data buffer to the first interface over a first channel, and
transmit the data from the data buffer with associated trace information for the data to the first memory device over a second channel;
a second interface; and
a second DMA controller communicably coupled to the first processing resource, and configured to:
transmit the data with the associated trace information from the first memory device to the second interface.