US 12,111,777 B2
Multiple pin configurations of memory devices
Junichi Sato, Yokohama (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 16, 2021, as Appl. No. 17/553,525.
Application 17/553,525 is a continuation of application No. 16/829,890, filed on Mar. 25, 2020, granted, now 11,243,896.
Prior Publication US 2022/0107906 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/38 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/1668 (2013.01) 7 Claims
OG exemplary drawing
 
3. A device, comprising:
memory cells;
a communication interface;
an integrated circuit package configured to enclose the memory cells and the communication interface; and
a plurality of connectors coupled to the communication interface to provide connections from the communication interface to outside of the integrated circuit package;
wherein the communication interface is adaptable to use the plurality of connectors in a first configuration to access the memory cells from the outside of the integrated circuit package at a first speed and to use the plurality of connectors in a second configuration to access the memory cells from the outside of the integrated circuit package at a second speed different from the first speed;
wherein the plurality of connectors includes a first subset and a second subset different from the first subset;
wherein when in the first configuration, the communication interface is configured to provide access to the memory cells using an entire set of the plurality of connectors at the first speed; and
wherein when in the first configuration, a first connector in the plurality of connectors is configured to transmit a first type of communications; and when in the second configuration, the first connector in the plurality of connectors is configured to transmit a second type of communications different from the first type.