US 12,111,775 B2
Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs
Duane E. Galbi, Wayland, MA (US); Matthew J. Adiletta, Bolton, MA (US); Hugh Wilkinson, Newton, MA (US); and Patrick Connor, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 25, 2021, as Appl. No. 17/212,722.
Claims priority of provisional application 63/130,672, filed on Dec. 26, 2020.
Prior Publication US 2021/0209035 A1, Jul. 8, 2021
Int. Cl. G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/1621 (2013.01) [G06F 13/1668 (2013.01); G06F 13/409 (2013.01); G06F 13/4221 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least two processing units comprising at least two processor sockets and
a memory hub coupled to the at least two processing units, the memory hub comprising a home agent, wherein:
the home agent of the memory hub is to maintain cache coherency among the at least two processing units,
the cache coherency among the at least two processing units comprises access a copy of modified content of a cache line,
the at least two processor sockets comprise at least two central processing units (CPUs),
the at least two CPUs comprise cores, and
to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub.