US 12,111,770 B2
Silent cache line eviction
Tony M. Brewer, Plano, TX (US); and Dean E. Walker, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/823,408.
Prior Publication US 2024/0070083 A1, Feb. 29, 2024
Int. Cl. G06F 12/0891 (2016.01); G06F 9/38 (2018.01)
CPC G06F 12/0891 (2013.01) [G06F 9/3816 (2013.01); G06F 2212/7209 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an interface configured to receive a memory operation from an external entity;
a cache including a cache line; and
processing circuitry configured to:
receive a memory operation via the interface, the memory operation establishing data and metadata in the cache line, wherein the metadata is cache coherency metadata;
store the metadata in a memory element that corresponds to the cache line;
identify an eviction trigger to evict the cache line;
compare, in response to the eviction trigger, current metadata of the cache line with the metadata in the memory element to determine whether the metadata has changed; and
evict the cache line without writing the metadata to backing memory in response to the metadata being unchanged.