US 12,111,769 B2
Validity mapping techniques
Xing Wang, Shanghai (CN); Zhen Gu, Shanghai (CN); Xu Zhang, Shanghai (CN); and Liping Xu, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/630,453
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Mar. 16, 2021, PCT No. PCT/CN2021/081140
§ 371(c)(1), (2) Date Jan. 26, 2022,
PCT Pub. No. WO2022/193143, PCT Pub. Date Sep. 22, 2022.
Prior Publication US 2023/0359563 A1, Nov. 9, 2023
Int. Cl. G06F 12/0873 (2016.01)
CPC G06F 12/0873 (2013.01) 24 Claims
OG exemplary drawing
 
2. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and operable to cause the memory system to:
receive a command associated with data having a corresponding set of physical addresses;
identify whether the set of physical addresses is a set of consecutive physical addresses;
set a flag in an entry of a change log associated with a mapping based at least in part on the identifying, the flag indicating whether physical addresses of the set of physical addresses are consecutive, the change log indicating changes to entries in the mapping, and the mapping indicating whether data stored at the physical addresses is valid; and
set the entry of the change log to indicate an update to a set of entries of the mapping based at least in part on identifying that the physical addresses of the set of physical addresses are consecutive.