US 12,111,768 B2
Methods and devices for controlling memory handling
Amir Roozbeh, Stockholm (SE); Alireza Farshin, Stockholm (SE); Dejan Kostic, Solna (SE); and Gerald Q Maguire, Jr., Stockholm (SE)
Assigned to Telefonaktiebolaget LM Ericsson (publ), Stockholm (SE)
Appl. No. 17/427,626
Filed by Telefonaktiebolaget LM Ericsson (publ), Stockholm (SE)
PCT Filed Feb. 13, 2020, PCT No. PCT/SE2020/050161
§ 371(c)(1), (2) Date Jul. 30, 2021,
PCT Pub. No. WO2020/167234, PCT Pub. Date Aug. 20, 2020.
Claims priority of provisional application 62/805,552, filed on Feb. 14, 2019.
Prior Publication US 2022/0100667 A1, Mar. 31, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 9/455 (2018.01); G06F 12/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0846 (2016.01); G06F 12/0871 (2016.01); G06F 12/0873 (2016.01)
CPC G06F 12/0871 (2013.01) [G06F 9/45558 (2013.01); G06F 12/0646 (2013.01); G06F 12/0811 (2013.01); G06F 12/0846 (2013.01); G06F 12/0873 (2013.01); G06F 2009/45583 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for controlling memory handling in a processing system comprising a cache and a plurality of processing units, wherein the cache is a last level cache shared among the plurality of processing units and wherein the last level cache has a plurality of cache portions allocated respectively to corresponding processing units of the plurality of processing units, in which a first cache portion of the plurality of cache portions is allocated to a first processing unit of the plurality of processing units, the method comprising:
obtaining first information pertaining to:
an allocation of a first memory portion of a memory to a first application;
an allocation of the first processing unit of the plurality of processing units to the first application; and
an association between the first cache portion of the plurality of cache portions to the first memory portion and the first processing unit;
receiving information regarding transfer of the first application running on the first processing unit to another processing unit of the plurality of processing units;
determining whether a reconfiguration of a mapping configuration of the first memory portion to the first cache portion is required, based on the received information regarding the transfer of the first application running on the first processing unit to the other processing unit;
reconfiguring the mapping configuration of the first memory portion to a different cache portion from the first cache portion, based on a determination that a reconfiguration of the mapping configuration is required; but retaining the mapping configuration of the first memory portion to the first cache portion, based on a determination that the reconfiguration of the mapping configuration is not required; and
controlling transfer of first data associated with the first application between the first memory portion and the other processing unit via use of the different cache portion, when reconfiguration of the mapping configuration of the first memory portion to the different cache portion is required.