US 12,111,764 B2
Forward caching memory systems and methods
Harold Robert George Trout, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 15, 2022, as Appl. No. 17/672,365.
Application 17/672,365 is a continuation of application No. 16/428,154, filed on May 31, 2019, granted, now 11,281,585.
Claims priority of provisional application 62/725,027, filed on Aug. 30, 2018.
Prior Publication US 2022/0171709 A1, Jun. 2, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0842 (2016.01); G06F 12/0855 (2016.01); G06F 12/0897 (2016.01); G06F 13/16 (2006.01); G06F 16/901 (2019.01)
CPC G06F 12/0859 (2013.01) [G06F 12/0842 (2013.01); G06F 12/0897 (2013.01); G06F 13/1684 (2013.01); G06F 16/901 (2019.01)] 20 Claims
OG exemplary drawing
 
9. A method comprising:
storing, by a memory system of a computing system coupled to a processing system of the computing system via a system bus, a first target data bits in a first data field of a first data record in a main memory array of the memory system;
storing, by the memory system, a second target data bits in a first data field of a second data record in the main memory array;
storing, by the memory system, a first index entry of an index table in an index table memory array of the memory system, wherein the first index entry is indicative of a storage location of the first data field of the first data record in the main memory array;
storing, by the memory system, a second index entry of the index table in the index table memory array, wherein the second index entry is indicative of a storage location of the first data field of the second data record in the main memory array, and wherein a storage location of the first index entry is associated with a storage location of the second index entry in the index table based at least in part on an interrelationship between values of the first target data bits and the second target data bits;
receiving, by the memory system, a memory access request from a processor of the processing system targeting the first target data bits;
predicting, by a memory controller of the memory system, that a subsequent memory access request from the processor will target the second target data bits based on storing the first index entry and the second index entry on associated storage locations in the index table based at least in part on the interrelationship between the values of the first target data bits and the second target data bits; and
providing, by the memory system, the first target data bits and the second target data bits to the processing system in response to receiving the memory access request and based on the prediction.