US 12,111,762 B2
Dynamic inclusive last level cache
Ayan Mandal, Bangaluru (IN); Leon Polishuk, Haifa (IL); Oz Shitrit, Tel Aviv (IL); and Joseph Nuzman, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/130,676.
Prior Publication US 2022/0197797 A1, Jun. 23, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/128 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 12/0815 (2013.01); G06F 12/128 (2013.01); G06F 2212/1032 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a core; and
a cache controller coupled to the core, the cache controller including circuitry to:
increment a counter value when a hit in a next level cache corresponds to an eviction from a core cache;
perform an evaluation to test for a condition wherein:
a current data hit corresponds to another eviction from the core cache, the current data hit comprising data from a working set; and
the counter value is greater than a threshold;
wherein, where the evaluation indicates a presence of the condition, the circuitry is further to:
identify the data from the working set for dynamic inclusion in the next level cache;
send a shared copy of the identified data to a requesting core of one or more processor cores;
maintain a copy of the identified data in the next level cache; and
set a snoop filter to indicate that the requesting core is valid for the current data hit.