US 12,111,758 B2
Synchronized request handling at a memory device
Tony M. Brewer, Plano, TX (US); and Dean E. Walker, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/899,197.
Prior Publication US 2024/0070060 A1, Feb. 29, 2024
Int. Cl. G06F 12/02 (2006.01); G06F 12/0831 (2016.01); G06F 12/0893 (2016.01)
CPC G06F 12/0238 (2013.01) [G06F 12/0833 (2013.01); G06F 12/0893 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a set of cache lines;
an interface to receive that indicates a memory address corresponding to the set of cache lines, the memory address corresponding to a single cache line in the set of cache lines, the apparatus maintaining a deferred list for the set of cache lines and a set of lists, each member of the set of lists corresponding to one cache line in the set of cache lines; and
processing circuitry configured to:
test the deferred list to determine that the deferred list is not empty; and
place the request in the deferred list.