US 12,111,726 B2
Error rates for memory with built in error correction and detection
Monish Shah, Sammamish, WA (US)
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Mar. 14, 2023, as Appl. No. 18/121,062.
Application 18/121,062 is a continuation of application No. 17/326,927, filed on May 21, 2021, granted, now 11,640,334.
Prior Publication US 2023/0214295 A1, Jul. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0772 (2013.01); G06F 11/0793 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a write request to write data in a plurality of memory chips with built in error detection, wherein a number of memory chips included in the plurality of memory chips is based on a channel width for a data payload and a bit-width for each memory chip of the plurality of memory chips;
determining parity bits for the data;
storing the data in a subset of the plurality of memory chips, wherein storing the data in the subset of the plurality of memory chips is based on the bit-width for each memory chip; and
storing the parity bits in one memory chip of the plurality of memory chips, wherein the one memory chip is different from the subset of the plurality of memory chips.