US 12,111,725 B2
Read retry scratch space
Rahul Mitchell Jairaj, Boise, ID (US); Mark A. Hawes, Boise, ID (US); and Terry M. Grunzke, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 17, 2023, as Appl. No. 18/111,280.
Application 18/111,280 is a continuation of application No. 16/960,527, granted, now 11,586,498, previously published as PCT/US2019/013026, filed on Jan. 10, 2019.
Claims priority of provisional application 62/617,057, filed on Jan. 12, 2018.
Prior Publication US 2023/0205628 A1, Jun. 29, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G06F 11/30 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0772 (2013.01); G06F 11/1048 (2013.01); G06F 11/1489 (2013.01); G06F 11/3037 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array having multiple blocks of memory cells; and
a memory controller operably coupled to the memory array, the memory controller configured to perform operations comprising:
in response to a detected error in data stored on the memory array corresponding to a memory operation, recover data corresponding to the detected error using one of a set of read offset values; and
load the one of the set of read offset values used to recover data corresponding to the detected error in a scratch space of the memory array as a custom read offset value for a subsequent memory operation.