US 12,111,724 B2
Redundant array management techniques
Chun Sum Yeung, San Jose, CA (US); Jonathan S. Parry, Boise, ID (US); Deping He, Boise, ID (US); Xiangang Luo, Fremont, CA (US); and Reshmi Basu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 19, 2022, as Appl. No. 17/648,395.
Claims priority of provisional application 63/162,141, filed on Mar. 17, 2021.
Prior Publication US 2022/0300374 A1, Sep. 22, 2022
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1076 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a volatile memory device;
a non-volatile memory device;
a first redundant array controller of a redundant array of independent nodes associated with the non-volatile memory device;
a second redundant array controller of the redundant array of independent nodes; and
processing circuitry coupled with the volatile memory device, the non-volatile memory device, the first redundant array controller, and the second redundant array controller, the processing circuitry configured to cause the memory system to:
receive a first write command associated with writing first data to a first type of memory cell;
generate, using the first redundant array controller, first parity data corresponding to the first data, the first parity data associated with the redundant array of independent nodes;
receive a second write command associated with writing second data to a second type of memory cell different than the first type of memory cell;
generate, using the second redundant array controller different than the first redundant array controller, second parity data corresponding to the second data, the second parity data associated with the redundant array of independent nodes; and
store the second parity data in the volatile memory device coupled with the first redundant array controller and the second redundant array controller.