US 12,111,719 B2
Remote scalable machine check architecture
Vilas K. Sridharan, Boxborough, MA (US); Magiting Talisayon, Boxborough, MA (US); Srikanth Masanam, Hyderabad (IN); and Dean A. Liberty, Nashua, NH (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/854,788.
Prior Publication US 2024/0004750 A1, Jan. 4, 2024
Int. Cl. G06F 11/07 (2006.01)
CPC G06F 11/0787 (2013.01) [G06F 11/0709 (2013.01); G06F 11/0721 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a remote processing circuit;
wherein the remote processing circuit is configured to:
detect an error;
store error log information corresponding to the error in a first storage location reserved for the remote processing circuit, wherein an operating system executed by a host processing circuit does not have access to the first storage location;
retrieve a target address pointing to a second storage location different from the first storage location, wherein the second storage location is accessible by the host processing circuit; and
write to the second storage location, using the target address, a message indicating the error has occurred.