US 12,111,716 B2
Device and method for efficient transitioning to and from reduced power state
Mihir Shaileshbhai Doctor, Santa Clara, CA (US); Alexander J. Branover, Boxborough, MA (US); Benjamin Tsien, Santa Clara, CA (US); Indrani Paul, Austin, TX (US); Christopher T. Weaver, Boxborough, MA (US); Thomas J. Gibney, Boxborough, MA (US); Stephen V. Kosonocky, Fort Collins, CO (US); and John P. Petry, San Diego, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Apr. 21, 2023, as Appl. No. 18/304,849.
Application 18/304,849 is a continuation of application No. 17/483,698, filed on Sep. 23, 2021, granted, now 11,703,937.
Prior Publication US 2023/0350484 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3287 (2013.01) [G06F 1/3265 (2013.01); G06F 1/3278 (2013.01); G06F 1/3296 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing device comprising:
a plurality of components having assigned registers used to store data to execute a program; and
a power management controller, in communication with the plurality of components, and configured to:
receive an indication that the plurality of components are idle;
execute a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component; and
execute a process to exit the component from the reduced power state in response to the component being active.