a core unit having a first core to support out-of-order execution of instructions, including a first cache memory, a second core to support in-order execution of instructions including a second cache memory, and a shared cache memory to be shared by at least the first core and the second core;

a graphics processing unit (GPU) to execute a graphics workload;

a memory controller;

a communication bus coupled to the core unit, the communication bus to couple the core unit and the GPU, the communication bus comprising a cache coherent interconnect;

a static random access memory;

an interface to interface the SoC with another device via a Peripheral Component Interconnect Express (PCIE) protocol;

a first workload monitor to determine a core workload of the core unit;

a second workload monitor to determine the graphics workload of the GPU;

a third workload monitor to determine a bus workload for the communication bus; and

a power controller to reduce a power consumption of at least the core unit if a thermal value of the SoC exceeds a thermal design power (TDP) limit for the SoC, wherein in a first scenario the power controller is to increase a frequency for the GPU when the graphics workload is greater than a graphics threshold and reduce the frequency of the core unit, and in a second scenario to increase a frequency for the core unit and the communication bus and reduce the frequency of the GPU,

wherein the power controller is to receive the bus workload and to dynamically balance power between the core unit and the communication bus based on the TDP limit and a comparison between the bus workload and a bus threshold, and

wherein the power controller, in response to operation of the SoC at the TDP limit, is to increase frequency for the communication bus and cap the frequency for the core unit if the bus workload is greater than the bus threshold, and decrease the frequency for the communication bus and increase the frequency for the core unit if the bus workload is less than the bus threshold.