US 12,111,684 B2
Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module
Douglas J. Malone, Pleasant Valley, NY (US); Andreas H. A. Arp, Nufringen (DE); Franklin M. Baez, Fishkill, NY (US); Daniel M. Dreps, Georgetown, TX (US); Jason Lee Frankel, Wappingers Falls, NY (US); Chad Andrew Marquart, Austin, TX (US); Ching Lung Tong, Highland Mills, NY (US); and Lily Jielu Zhang, Wappingers Falls, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 24, 2023, as Appl. No. 18/455,101.
Application 18/455,101 is a division of application No. 17/471,442, filed on Sep. 10, 2021, granted, now 11,775,004.
Prior Publication US 2023/0393610 A1, Dec. 7, 2023
Int. Cl. G06F 1/12 (2006.01); G06F 1/08 (2006.01); H03L 7/085 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/08 (2013.01); H03L 7/085 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A two-chip die module with minimal chip-to-chip clock skew, comprising:
a common substrate;
first and second chips operably disposed on the common substrate to be communicative in parallel with one another;
a single phase lock loop (PLL) disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips,
PLL signals of the PLL to the first and second chips being nearly equal and clock sample signals of the first and second chips being nearly equal,
wherein:
the PLL comprises first and second differential drivers respectively associated with the first and second chips,
the first and second chips each comprise a differential receiver and a clocking logic assembly connected in series with the first and second differential drivers, respectively, and
a distance from the first differential driver to the differential receiver of the first chip is equal or nearly equal to a distance from the second differential driver to the differential receiver of the second chip.