	US 12,111,354 B2
	Detection circuit of clock anomaly and method, clock circuit, chip and radar
Yumin Liao, Shenzhen (CN); Junling Zang, Shenzhen (CN); and Yueqing Yang, Shenzhen (CN)
Assigned to SUTENG INNOVATION TECHNOLOGY CO., LTD., Shenzhen (CN)
Filed by SUTENG INNOVATION TECHNOLOGY CO., LTD., Shenzhen (CN)
Filed on Apr. 5, 2023, as Appl. No. 18/131,344.
Claims priority of application No. 202210364370.8 (CN), filed on Apr. 8, 2022.
Prior Publication US 2023/0324460 A1, Oct. 12, 2023
Int. Cl. G01R 31/317 (2006.01)

CPC G01R 31/31727 (2013.01)

9 Claims

1. A detection circuit of clock anomaly, comprising:

a first clock frequency determining unit, configured to determine a first clock frequency of a received first clock signal;

a reference determining unit, configured to determine a reference corresponding to the first clock signal, wherein the reference is determined based on at least one of a second clock signal or a timestamp; and

a clock anomaly detection unit, connected to the first clock frequency determining unit and the reference determining unit separately and configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference;

wherein the reference determining unit comprises a first reference time period determining circuit, configured to determine a first reference time period, wherein the first reference time period is a time period during which a number of pulses of the second clock signal reaches a first count value;

wherein the first clock frequency determining unit comprises a first counter, connected to the clock anomaly detection unit and configured to: perform pulse counting on the first clock signal within the first reference time period to obtain a second count value, and transmit the second count value to the clock anomaly detection unit;

wherein the first reference time period determining circuit comprises:

a second counter, connected to the clock anomaly detection unit and configured to: in response to a first enabling signal, perform pulse counting on the second clock signal until reaching a preset first count value, transmit the first count value to the clock anomaly detection unit, and output a counting completion signal; and

a counting control unit, connected to the first counter and the second counter separately and configured to: output the first enabling signal to the first counter and the second counter, output a counting ending instruction to the first counter in response to the counting completion signal, and send a second enabling signal to the clock anomaly detection unit, wherein the counting control unit comprises a delay control circuit.