CPC H04W 72/569 (2023.01) [H04W 72/0446 (2013.01); H04W 72/1268 (2013.01); H04W 72/23 (2023.01)] | 20 Claims |
1. A core network apparatus comprising
at least one processor, and
at least one non-transitory memory storing instructions, that when executed by the at least one processor, cause the core network apparatus to:
receive data units from at least one network access apparatus,
wherein each data unit is labelled with a respective priority level; and
withhold from transmitting a data unit labelled with a relatively low priority level in accordance with a predetermined schedule,
wherein the predetermined schedule is based on
a slot timing for data arriving at the at least one network access apparatus for communication upstream, and
a predetermined delay time in forwarding the data from the at least one network access apparatus to the core network apparatus.
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