US 11,784,835 B2
Detection and mitigation of unstable cells in unclonable cell array
Sudhir Shrikantha Kudva, Dublin, CA (US); Nikola Nedovic, San Jose, CA (US); Carl Thomas Gray, Apex, NC (US); and Stephen G Tell, Chapel Hill, NC (US)
Assigned to NVIDIA CORP., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Sep. 21, 2021, as Appl. No. 17/481,154.
Application 17/481,154 is a continuation in part of application No. 17/184,396, filed on Feb. 24, 2021, granted, now 11,411,563.
Prior Publication US 2022/0271952 A1, Aug. 25, 2022
Int. Cl. H04L 9/32 (2006.01); H04L 9/08 (2006.01)
CPC H04L 9/3278 (2013.01) [H04L 9/0825 (2013.01); H04L 9/0861 (2013.01); H04L 2209/12 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A circuit comprising:
a plurality of bit generating cells;
at least one characterization circuit coupled to influence outputs of the bit generating cells, the characterization circuit comprising:
a first inverter;
a second inverter;
at least one pass-gate circuit coupled between the first inverter and the second inverter;
logic to select and apply, based on varying an input and a bias of the first inverter, the outputs of a subset less than all of the bit generating cells.