CPC H04L 9/3278 (2013.01) [H04L 9/0825 (2013.01); H04L 9/0861 (2013.01); H04L 2209/12 (2013.01)] | 19 Claims |
1. A circuit comprising:
a plurality of bit generating cells;
at least one characterization circuit coupled to influence outputs of the bit generating cells, the characterization circuit comprising:
a first inverter;
a second inverter;
at least one pass-gate circuit coupled between the first inverter and the second inverter;
logic to select and apply, based on varying an input and a bias of the first inverter, the outputs of a subset less than all of the bit generating cells.
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