US 11,784,792 B2
Secure software interface
Manuela Meier, Munich (DE); and Andreas Graefe, Munich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Sep. 29, 2020, as Appl. No. 16/948,689.
Prior Publication US 2022/0103342 A1, Mar. 31, 2022
Int. Cl. H04L 9/06 (2006.01); H04L 9/08 (2006.01); G06F 21/72 (2013.01)
CPC H04L 9/0643 (2013.01) [G06F 21/72 (2013.01); H04L 9/0894 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A system, comprising:
a first processing component arranged in a secure domain of the system;
a second processing component arranged in a non-secure domain located outside of the secure domain of the system;
one or more hardware accelerators to perform operations in association with providing communication security for the system, wherein the first processing component and the second processing component are configured to share the one or more hardware accelerators,
wherein the first processing component is configured to access the one or more hardware accelerators via a first channel configured in the secure domain for transmitting first information to the one or more hardware accelerators, and
wherein the second processing component is configured to access the one or more hardware accelerators via a second channel configured in the non-secure domain for transmitting second information to the one or more hardware accelerators;
an access restriction component arranged in the non-secure domain and coupled to the second channel between the second processing component and the one or more hardware accelerators, wherein the access restriction component is configured to manage access of the second processing component to the one or more hardware accelerators by managing the access of the second processing component to the second channel,
wherein the second processing component is configured to access the one or more hardware accelerators via the access restriction component and via the second channel; and
a mapping component arranged in the non-secure domain and configured to dynamically map the first channel and the second channel to the one or more hardware accelerators.