US 11,784,651 B2
Circuitry and methods for fractional division of high-frequency clock signals
Ravichandar Reddy Geetla, Austin, TX (US); Deependra Kumar Jain, Noida (IN); Gaurav Agrawal, Aligarh (IN); and Ravi Kumar, Noida (IN)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Oct. 27, 2021, as Appl. No. 17/512,231.
Prior Publication US 2023/0126891 A1, Apr. 27, 2023
Int. Cl. H03L 7/099 (2006.01); H03L 7/081 (2006.01); H03L 7/197 (2006.01); H03M 3/00 (2006.01)
CPC H03L 7/0992 (2013.01) [H03L 7/0814 (2013.01); H03L 7/0995 (2013.01); H03L 7/1974 (2013.01); H03M 3/30 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an oscillator configured to provide a plurality of clock signals, including a first clock signal having a first period and a first frequency, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period, wherein the predetermined fractional amount is between zero and one;
a sigma-delta modulator; and
a multiphase frequency divider configured to receive the plurality of clock signals and provide a divided clock output which has a second frequency, wherein the first frequency divided by the second frequency is capable of being an integer or a non-integer, the multiphase frequency divider comprising:
an integer frequency divider configured to provide the divided clock output based on a modified clock input;
a clock selector configured to provide a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output, wherein:
the current clock and the next clock are different selected clocks signals of the plurality of clock signals,
the next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by the sigma-delta modulator,
a transition in providing the next clock rather than the current clock as the modified clock input occurs in response to a falling edge of the divided clock output,
the selected fractional phase shift amount is between zero and one and corresponds to a multiple of the predetermined fractional amount of the first period, and
the clock selector comprises pulse extension circuitry configured to extend a pulse of the modified clock input such that the pulse of the modified clock input during which the transition occurs begins synced with a rising edge of a pulse of the current clock and ends synced with a falling edge of a pulse of the next clock.