US 11,784,287 B2
Surface potential barrier for surface loss reduction at mesa sidewalls of micro-LEDs
Alexander Tonkikh, Cork (IE); Michael Grundmann, Kirkland, WA (US); and Alexander Franke, Cork (IE)
Assigned to META PLATFORMS TECHNOLOGIES, LLC, Menlo Park, CA (US)
Filed by Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed on May 26, 2021, as Appl. No. 17/331,306.
Prior Publication US 2022/0384679 A1, Dec. 1, 2022
Int. Cl. H01L 33/24 (2010.01); H01L 33/06 (2010.01); H01L 33/30 (2010.01); H01L 33/46 (2010.01)
CPC H01L 33/24 (2013.01) [H01L 33/06 (2013.01); H01L 33/30 (2013.01); H01L 33/46 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A micro-light emitting diode (micro-LED) device comprising a mesa structure, the mesa structure comprising:
a first set of one or more semiconductor layers;
an active layer on the first set of one or more semiconductor layers and configured to emit light;
a second set of one or more semiconductor layers on the active layer; and
a dielectric layer in sidewall regions of the mesa structure,
wherein a first thickness of a center region of the second set of one or more semiconductor layers is higher than a second thickness of a sidewall region of the second set of one or more semiconductor layers, such that a distance from a surface of the sidewall region of the second set of one or more semiconductor layers to the active layer is less than a distance from a surface of the center region of the second set of one or more semiconductor layers to the active layer to form a surface potential-induced lateral potential barrier at a sidewall region of the active layer caused by a surface potential at the sidewall region of the second set of one or more semiconductor layers;
wherein the second set of one or more semiconductor layers includes a p-type semiconductor layer and an undoped or unintentionally doped semiconductor layer between the p-type semiconductor layer and the active layer; and
wherein the p-type semiconductor layer is partially or fully removed at the sidewall region of the second set of one or more semiconductor layers to form a step structure.