US 11,784,243 B2
Oxide-nitride-oxide stack having multiple oxynitride layers
Sagy Charel Levy, Zichron Yaakov (IL); Krishnaswamy Ramkumar, San Jose, CA (US); Fredrick Jenne, Mountain House, CA (US); and Sam G Geha, Cupertino, CA (US)
Assigned to LONGITUDE FLASH MEMORY SOLUTIONS LTD, Dublin (IE)
Filed by LONGITUDE FLASH MEMORY SOLUTIONS LTD, Dublin (IE)
Filed on Dec. 2, 2021, as Appl. No. 17/541,029.
Application 17/541,029 is a division of application No. 16/726,582, filed on Dec. 24, 2019, granted, now 11,222,965.
Application 16/726,582 is a continuation of application No. 15/993,224, filed on May 30, 2018, granted, now 10,896,973, issued on Jan. 19, 2021.
Application 15/993,224 is a continuation of application No. 15/189,668, filed on Jun. 22, 2016, granted, now 10,374,067, issued on Aug. 6, 2019.
Application 15/189,668 is a continuation of application No. 13/436,872, filed on Mar. 31, 2012, granted, now 9,449,831, issued on Sep. 20, 2016.
Application 13/436,872 is a continuation in part of application No. 11/811,958, filed on Jun. 13, 2007, abandoned.
Claims priority of provisional application 60/931,947, filed on May 25, 2007.
Prior Publication US 2022/0093773 A1, Mar. 24, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/28 (2006.01); G11C 16/04 (2006.01); H01L 29/792 (2006.01); B82Y 10/00 (2011.01); H01L 29/423 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66833 (2013.01) [B82Y 10/00 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01); H01L 29/7833 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method to form a non-volatile memory device, comprising:
providing a semiconductor substrate;
forming a lower dielectric layer over the semiconductor substrate;
forming a memory control gate layer on the lower dielectric layer;
forming an upper dielectric layer on the memory control gate layer, wherein the memory control gate layer is formed immediately adjacent to and sandwiched between the lower dielectric layer and the upper dielectric layer;
forming a first opening through a stack of the upper dielectric layer, the memory control gate layer and the lower dielectric layer;
forming a blocking dielectric layer, a charge storing layer and a tunnel dielectric layer in the first opening, wherein forming the charge storing layer comprising forming a first oxygen-rich silicon oxynitride layer closer to the tunnel dielectric layer and forming a second oxygen-lean silicon oxynitride layer closer to the blocking dielectric layer;
removing a blocking dielectric layer, a charge storing layer and a tunnel dielectric layer from a bottom surface of the first opening;
forming a semiconductor layer in the opening, wherein a part of the semiconductor layer forming a vertical channel region of the non-volatile memory device;
forming a dielectric filler material in the opening such that the dielectric filler material is surrounded by the semiconductor layer within the opening; and
incorporating carbon into the second oxygen-lean silicon oxynitride layer.