US 11,784,239 B2
Subfin leakage suppression using fixed charge
Sean T. Ma, Portland, OR (US); Aaron D. Lilak, Beaverton, OR (US); Justin R. Weber, Portland, OR (US); Harold W. Kennel, Portland, OR (US); Willy Rachmady, Beaverton, OR (US); Gilbert W. Dewey, Beaverton, OR (US); Cheng-Ying Huang, Portland, OR (US); Matthew V. Metz, Portland, OR (US); Jack T. Kavalieros, Portland, OR (US); Anand S. Murthy, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/341,020
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 14, 2016, PCT No. PCT/US2016/066436
§ 371(c)(1), (2) Date Apr. 10, 2019,
PCT Pub. No. WO2018/111250, PCT Pub. Date Jun. 21, 2018.
Prior Publication US 2020/0044059 A1, Feb. 6, 2020
Int. Cl. H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 29/0665 (2013.01); H01L 29/408 (2013.01); H01L 29/785 (2013.01); H01L 29/7855 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a transistor arrangement that includes:
a fin stack of one or more semiconductor materials having a shape of a fin extending away from a base, the fin comprising a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion;
a gate wrapping around the channel portion of the fin;
a liner on sidewalls of the subfin portion of the fin; and
an insulator material surrounding the sidewalls,
wherein the liner includes fixed charges and is between the sidewalls and the insulator material, the insulator material is in contact with the base, and a portion of the liner that is farthest away from the base is at a same distance from the base as a portion of the gate that is closest to the base.